Описание динамического триггера и дешифратора на языке VHDL

Динамический триггер:

ENTITY ff IS

PORT (RST,CLK,WE: IN std_logic;

D_IN: IN std_logic;

D: OUT std_logic);

END ff;

ARCHITECTURE DataFlow OF ff IS

BEGIN

D<= '0' WHEN RST='1' ELSE

D_IN WHEN (CLK='1') AND (CLK' event) AND (WE='1');

END DataFlow;

Дешифратор:

LIBRARY ieee; --Описание подключаемых библиотек

USE ieee.std_logic_1164. ALL;

ENTITY decoder IS

PORT (inp: IN std_logic_vector(2 DOWNTO 0);

outp: OUT std_logic_vector(7 DOWNTO 0));

END decoder;

ARCHITECTURE DataFlow OF decoder IS

BEGIN

outp(0) <= '1' WHEN inp = "000" ELSE '0';

outp(1) <= '1' WHEN inp = "001" ELSE '0';

outp(2) <= '1' WHEN inp = "010" ELSE '0';

outp(3) <= '1' WHEN inp = "011" ELSE '0';

outp(4) <= '1' WHEN inp = "100" ELSE '0';

outp(5) <= '1' WHEN inp = "101" ELSE '0';

outp(6) <= '1' WHEN inp = "110" ELSE '0';

outp(7) <= '1' WHEN inp = "111" ELSE '0';

END DataFlow;

ИЛИ

LIBRARY ieee;

USE ieee.std_logic_1164. ALL;

ENTITY decoder IS

PORT (inp: IN std_logic_vector(2 DOWNTO 0);

outp: OUT std_logic_vector(7 DOWNTO 0));

END decoder;

ARCHITECTURE behave OF decoder IS

BEGIN

PROCESS (inp) BEGIN

CASE inp IS

WHEN "000" => outp <= "00000001";

WHEN "001" => outp <= "00000010";

WHEN "010" => outp <= "00000100";

WHEN "011" => outp <= "00001000";

WHEN "100" => outp <= "00010000";

WHEN "101" => outp <= "00100000";

WHEN "110" => outp <= "01000000";

WHEN "111" => outp <= "10000000";

WHEN OTHERS => outp <= "XXXXXXXX";

END CASE;

END PROCESS;

END behave;

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