Описание шифратора и драйвера шины на языке VHDL.

Шифратор:

ENTITY encoder IS

PORT (in1: IN std_logic_vector(7 DOWNTO 0);

out1: OUT std_logic_vector(2 DOWNTO 0));

END encoder;

ARCHITECTURE behave OF encoder IS

BEGIN

PROCESS (in1)

BEGIN

IF in1(7) = '1' THEN out1 <= "111";

ELSIF in1(6) = '1' THEN out1 <= "110";

ELSIF in1(5) = '1' THEN out1 <= "101";

ELSIF in1(4) = '1' THEN out1 <= "100";

ELSIF in1(3) = '1' THEN out1 <= "011";

ELSIF in1(2) = '1' THEN out1 <= "010";

ELSIF in1(1) = '1' THEN out1 <= "001";

ELSIF in1(0) = '1' THEN out1 <= "000";

ELSE out1 <= "XXX";

END IF;

END PROCESS;

END behave;

ИЛИ

ENTITY encoder IS

PORT (a, b, c, d, e, f, g, h: IN std_logic;

out2, out1, out0: OUT std_logic);

END encoder;

ARCHITECTURE behave OF encoder IS

BEGIN

PROCESS (a, b, c, d, e, f, g, h)

VARIABLE inputs: std_logic_vector (7 DOWNTO 0);

VARIABLE i: INTEGER;

BEGIN

INPUTS:= (h, g, f, e, d, c, b, a);

i:= 7;

WHILE i >= 0 AND inputs(i) /= '1' LOOP

i:= i - 1;

END LOOP;

IF (i < 0) THEN

i:= 0;

END IF;

-- conv_std_logic_vector (i, 3) - функция преобразования

-- переменной типа integer в сигнал типа std_logic_vector

-- Второй аргумент определяет размер вектора.

(out2, out1, out0) <= conv_std_logic_vector (i, 3);

END process;

END behave;

-- Синтезируемое описание драйвера шины

LIBRARY ieee;

USE ieee.std_logic_1164. ALL;

ENTITY tristate2 IS

PORT (input3, input2, input1, input0: IN std_logic_vector (7 DOWNTO 0);

enable: IN std_logic_vector (3 DOWNTO 0);

output: OUT std_logic_vector (7 DOWNTO 0));

END tristate2;

ARCHITECTURE multiple_drivers of tristate2 IS

BEGIN

output <= input3 WHEN enable(3) = '1' ELSE "ZZZZZZZZ";

output <= input2 WHEN enable(2) = '1' ELSE "ZZZZZZZZ";

output <= input1 WHEN enable(1) = '1' ELSE "ZZZZZZZZ";

output <= input0 WHEN enable(0) = '1' ELSE "ZZZZZZZZ";

END multiple_drivers;

-- Синтезируемое описание шинного формирователя

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY bidir IS

PORT (input_val, enable: IN std_logic;

output_val: OUT std_logic;

bidir_port: INOUT std_logic);

END bidir;

ARCHITECTURE tri_state OF bidir IS

BEGIN

bidir_port <= input_val WHEN enable = '1' ELSE 'Z';

output_val <= bidir_port;

END tri_state;

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